Datasheet

Rev. 4.00 Jun 06, 2006 page xli of liv
Figure 16.16 Flowchart for Slave Receive Mode (Example).................................................. 503
Figure 16.17 Flowchart for Slave Transmit Mode (Example)................................................ 504
Figure 16.18 Points for Attention Concerning Reading of Master Receive Data................... 511
Figure 16.19 Flowchart and Timing of Start Condition Instruction Issuance
for Retransmission............................................................................................. 512
Figure 16.20 Timing of Stop Condition Issuance................................................................... 513
Figure 16.21 IRIC Flag Clear Timing on WAIT Operation ................................................... 514
Figure 16.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode....................... 515
Figure 16.23 TRS Bit Setting Timing in Slave Mode............................................................. 516
Figure 16.24 Diagram of Erroneous Operation when Arbitration is Lost............................... 517
Figure 16.25 Note on Interrupt Occurrence in Slave Mode after ACKB = 1 Reception ........ 519
Figure 16.26 Notes on ICDR Reading with TRS = 1 Setting in Master Mode....................... 521
Figure 16.27 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode.......................... 521
Section 17 Host Interface [H8S/2138 Group]
Figure 17.1 Block Diagram of Host Interface....................................................................... 524
Figure 17.2 GA20 Output..................................................................................................... 538
Figure 17.3 HIRQ Output Flowchart.................................................................................... 542
Section 18 D/A Converter
Figure 18.1 Block Diagram of D/A Converter...................................................................... 544
Figure 18.2 D/A Conversion (Example)............................................................................... 549
Section 19 A/D Converter
Figure 19.1 Block Diagram of A/D Converter...................................................................... 552
Figure 19.2 ADDR Access Operation (Reading H'AA40) ................................................... 561
Figure 19.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ...... 563
Figure 19.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Selected) ............................................................................................................ 565
Figure 19.5 A/D Conversion Timing.................................................................................... 566
Figure 19.6 External Trigger Input Timing .......................................................................... 567
Figure 19.7 Example of Analog Input Protection Circuit..................................................... 569
Figure 19.8 Analog Input Pin Equivalent Circuit ................................................................. 569
Figure 19.9 A/D Conversion Precision Definitions (1)......................................................... 571
Figure 19.10 A/D Conversion Precision Definitions (2)......................................................... 571
Figure 19.11 Example of Analog Input Circuit ...................................................................... 572
Section 20 RAM
Figure 20.1 Block Diagram of RAM (H8S/2138, H8S/2134, H8S/2133) ............................ 573