Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 4.00 Jun 06, 2006 page 373 of 1004
REJ09B0301-0400
Overflow
TCNT TCSR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
Clock
select
Interrupt
control
Reset
control
Internal clock
source
Bus
interface
Module bus
Internal bus
WDT
WOVI
(interrupt request
signal)
Internal reset
signal
*
1
Internal NMI
(interrupt request
signal)
*
2
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
φ
SUB
/2
φ
SUB
/4
φ
SUB
/8
φ
SUB
/16
φ
SUB
/32
φ
SUB
/64
φ
SUB
/128
φ
SUB
/256
Notes: 1. For the internal reset signal, the reset of the WDT that overflowed first has priority.
2. The internal NMI interrupt request signal can be output independently by either WDT0 or
WDT1. The interrupt controller does not distinguish between NMI interrupt requests from
WDT0 and WDT1.
Figure 14.1 (b) Block Diagram of WDT1