Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 4.00 Jun 06, 2006 page 372 of 1004
REJ09B0301-0400
14.1.2 Block Diagram
Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1.
Overflow
WOVI
(interrupt request
signal)
Internal reset
signal
*
1
TCNT TCSR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
Clock
select
Internal clock
source
Bus
interface
Module bus
Internal bus
WDT
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
Internal NMI
interrupt request
signal
*
2
Interrupt
control
Reset
control
Notes: 1. For the internal reset signal, the reset of the WDT that overflowed first has priority.
2. The internal NMI interrupt request signal can be output independently by either WDT0 or
WDT1. The interrupt controller does not distinguish between NMI interrupt requests from
WDT0 and WDT1.
Figure 14.1 (a) Block Diagram of WDT0