Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 4.00 Jun 06, 2006 page 371 of 1004
REJ09B0301-0400
Section 14 Watchdog Timer (WDT)
14.1 Overview
The H8S/2138 Group and H8S/2134 Group have an on-chip watchdog timer with two channels
(WDT0, WDT1) for monitoring system operation. The WDT outputs an overflow signal if a
system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the
same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer mode, an interval timer interrupt is generated each time the counter overflows.
14.1.1 Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
 WOVI interrupt generation in interval timer mode
• Internal reset or internal interrupt generated when the timer counter overflows
 Choice of internal reset or NMI interrupt generation in watchdog timer mode
• Choice of 8 (WDT0) or 16 (WDT1) counter input clocks
 Maximum WDT interval: system clock period × 131072 × 256
 Subclock can be selected for the WDT1 input counter
 Maximum interval when the subclock is selected: subclock period × 256 × 256