Datasheet

Rev. 4.00 Jun 06, 2006 page xl of liv
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) .............................................. 429
Figure 15.9 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ...................................... 431
Figure 15.10 Sample Multiprocessor Serial Transmission Flowchart .................................... 432
Figure 15.11 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).......................... 434
Figure 15.12 Sample Multiprocessor Serial Reception Flowchart.......................................... 435
Figure 15.13 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).......................... 437
Figure 15.14 Data Format in Synchronous Communication................................................... 438
Figure 15.15 Sample SCI Initialization Flowchart ................................................................. 440
Figure 15.16 Sample Serial Transmission Flowchart ............................................................. 441
Figure 15.17 Example of SCI Operation in Transmission...................................................... 443
Figure 15.18 Sample Serial Reception Flowchart................................................................... 444
Figure 15.19 Example of SCI Operation in Reception ........................................................... 445
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations... 446
Figure 15.21 Block Diagram of IrDA Function...................................................................... 447
Figure 15.22 IrDA Transmit/Receive Operations................................................................... 448
Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode .................................. 453
Figure 15.24 Example of Synchronous Transmission by DTC .............................................. 454
Section 16 I
2
C Bus Interface [H8S/2138 Group Option]
Figure 16.1 Block Diagram of I
2
C Bus Interface.................................................................. 457
Figure 16.2 I
2
C Bus Interface Connections (Example: H8S/2138 Group Chip as Master)... 458
Figure 16.3 I
2
C Bus Data Formats (I
2
C Bus Formats)........................................................... 485
Figure 16.4 Formatless.......................................................................................................... 486
Figure 16.5 I
2
C Bus Data Format (Serial Format) ................................................................ 486
Figure 16.6 I
2
C Bus Timing.................................................................................................. 486
Figure 16.7 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)..... 489
Figure 16.8 (a) Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)........................................................................ 491
Figure 16.8 (b) Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1) (cont).............................................................. 491
Figure 16.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) .. 493
Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) .. 494
Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0)...................... 496
Figure 16.12 IRIC Setting Timing and SCL Control.............................................................. 497
Figure 16.13 Block Diagram of Noise Canceler..................................................................... 500
Figure 16.14 Flowchart for Master Transmit Mode (Example).............................................. 501
Figure 16.15 Flowchart for Master Receive Mode (Example) ............................................... 502