Datasheet

Section 13 Timer Connection [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 354 of 1004
REJ09B0301-0400
Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and
phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IVI signal at positive
phase by modifying TCONRI.
Bit 0
IVI Description
0 The IVI signal is low
1 The IVI signal is high
13.2.5 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13, MSTP12, and MSTP8 bits are set to 1, the 16-bit free-running timer, 8-bit
timer channels 0 and 1, and 8-bit timer channels X and Y and timer connection, respectively, halt
and enter module stop mode. See section 24.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 5—Module Stop (MSTP13): Specifies FRT module stop mode.
MSTPCRH
Bit 5
MSTP13 Description
0 FRT module stop mode is cleared
1 FRT module stop mode is set (Initial value)