Datasheet

Rev. 4.00 Jun 06, 2006 page xxxix of liv
Figure 12.10 Timing of Input Capture Signal (When Input Capture Input Signal Enters
while TICRR and TICRF Are Being Read)....................................................... 331
Figure 12.11 Switching of Input Capture Signal .................................................................... 331
Figure 12.12 Pulse Output (Example) .................................................................................... 334
Figure 12.13 Contention between TCNT Write and Clear ..................................................... 335
Figure 12.14 Contention between TCNT Write and Increment.............................................. 336
Figure 12.15 Contention between TCOR Write and Compare-Match.................................... 337
Section 13 Timer Connection [H8S/2138 Group]
Figure 13.1 Block Diagram of Timer Connection Facility................................................... 342
Figure 13.2 Timing Chart for PWM Decoding..................................................................... 356
Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) ......... 358
Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal).......................... 358
Figure 13.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided
Waveform Periods............................................................................................. 360
Figure 13.6 2fH Modification Timing Chart ........................................................................ 361
Figure 13.7 Fall Modification/IHI Synchronization Timing Chart....................................... 363
Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart............................................ 366
Figure 13.9 CBLANK Output Waveform Generation.......................................................... 369
Section 14 Watchdog Timer (WDT)
Figure 14.1 (a) Block Diagram of WDT0 .................................................................................. 372
Figure 14.1 (b) Block Diagram of WDT1 .................................................................................. 373
Figure 14.2 Format of Data Written to TCNT and TCSR (Example of WDT0) .................. 380
Figure 14.3 Operation in Watchdog Timer Mode................................................................. 382
Figure 14.4 Operation in Interval Timer Mode..................................................................... 383
Figure 14.5 Timing of OVF Setting...................................................................................... 383
Figure 14.6 Contention between TCNT Write and Increment.............................................. 384
Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.1 Block Diagram of SCI....................................................................................... 389
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)............................................ 419
Figure 15.3 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode) ....................................................................................... 421
Figure 15.4 Sample SCI Initialization Flowchart ................................................................. 422
Figure 15.5 Sample Serial Transmission Flowchart ............................................................. 423
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) .............................................. 425
Figure 15.7 Sample Serial Reception Data Flowchart.......................................................... 426