Datasheet

Section 13 Timer Connection [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 351 of 1004
REJ09B0301-0400
Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits
select the signal source for the CLO signal (clamp waveform).
Bit 6 Bit 1 Bit 0
ISGENE CLMOD1 CLMOD2 Description
0 0 0 The CL1 signal is selected (Initial value)
1 The CL2 signal is selected
1 0 The CL3 signal is selected
1
1 0 0 The CL4 signal is selected
1
10
1
13.2.4 Edge Sense Register (SEDGR)
Bit
Initial value
Read/Write
Notes: 1. Only 0 can be written, to clear the flags.
2. The initial value is undefined since it depends on the pin states.
7
VEDG
0
R/(W)
*
1
6
HEDG
0
R/(W)
*
1
5
CEDG
0
R/(W)
*
1
4
HFEDG
0
R/(W)
*
1
3
VFEDG
0
R/(W)
*
1
0
IVI
—
*
2
R
2
PREQF
0
R/(W)
*
1
1
IHI
—
*
2
R
SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection
input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI
signals.
The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The
initial value of the lower 2 bits is undefined, since it depends on the pin states.