Datasheet

Section 13 Timer Connection [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 348 of 1004
REJ09B0301-0400
Bit 5
CLOE Description
0 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the P64/FTIC/KIN4/CIN4 pin
(Initial value)
1 The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin
Bit 4
CBOE Description
0 The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin (Initial value)
1 In mode 1 (expanded mode with on-chip ROM disabled):
The P27/A15/PW15/CBLANK pin functions as the A15 pin
In modes 2 and 3 (modes with on-chip ROM enabled):
The P27/A15/PW15/CBLANK pin functions as the CBLANK pin
Bits 3 to 0—Output Synchronization Signal Inversion (HOINV, VOINV, CLOINV,
CBOINV): These bits select inversion of the output phase of the horizontal synchronization signal
(HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO),
and the blank waveform (CBLANK).
Bit 3
HOINV Description
0 The IHO signal is used directly as the HSYNCO output (Initial value)
1 The IHO signal is inverted before use as the HSYNCO output
Bit 2
VOINV Description
0 The IVO signal is used directly as the VSYNCO output (Initial value)
1 The IVO signal is inverted before use as the VSYNCO output
Bit 1
CLOINV Description
0 The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the CLAMPO
output (Initial value)
1 The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as the
CLAMPO output