Datasheet

Section 13 Timer Connection [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 342 of 1004
REJ09B0301-0400
13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the timer connection facility.
Edge
detection
Edge
detection
VSYNCI/ FTIA/TMIY
VFBACKI/ FTIB
FTIC FTID
Phase
inversion
Phase
inversion
Phase
inversion
phase inversion
phase
inversion
Phase
inversion
IVI
signal
selection
READ
flag
Edge
detection
Edge
detection
Edge
detection
Phase
inversion
Phase
inversion
Phase
inversion
READ
flag
IVI signal
FRT
input
selec-
tion
SET
sync
RES
VSYNC modify
FTIA
FTIB
FTIC
FTID
16-bit FRT
OCRA +VR, +VF
ICRD +1M, +2M
compare match
FTOA
CMA(R) CMA(F)
FTOB
CM2MCM1M
RESSET
2f H mask generation
2f H mask/flag
CBLANK waveform
generation
TMR1
input
selection
TMCI
8-bit TMR1
TMRI
CMB
TMO
SET
IVG signal
IVO signal
RES
VSYNC
generation
IVO
signal
selection
TMIY
signal
selection
FRT
output
selection
VSYNCO/ FTOA
TMRI/TMCI
TMO
8-bit TMRY
IHG signal
CBLANK
HSYNCO/ TMO1 TMOX
TMO1
output
selection
IHO
signal
selection
CL4 generation
CL4 signal
CLAMPO
/
FTIC
CL
signal
selection
PDC signal
PWM decoding
8-bit TMRX
CMB
TMO
CMA
ICR
ICR +1C
compare match
CLAMP waveform generation
TMCI TMRI
CM1C
CL1 signal CL2 signal CL3 signal
IHI signal
IHI
signal
selection
HSYNCI/ TMCI1 CSYNCI/ TMRI1 HFBACKI/ FTCI/TMIX
Figure 13.1 Block Diagram of Timer Connection Facility