Datasheet

Rev. 4.00 Jun 06, 2006 page xxxvii of liv
Figure 7.4 Correspondence between DTC Vector Address and Register Information ....... 173
Figure 7.5 Location of DTC Register Information in Address Space................................. 175
Figure 7.6 Memory Mapping in Normal Mode .................................................................. 176
Figure 7.7 Memory Mapping in Repeat Mode.................................................................... 177
Figure 7.8 Memory Mapping in Block Transfer Mode....................................................... 179
Figure 7.9 Memory Mapping in Chain Transfer................................................................. 180
Figure 7.10 DTC Operation Timing (Normal Mode or Repeat Mode)................................. 181
Figure 7.11 DTC Operation Timing (Block Transfer Mode, with Block Size of 2)............. 181
Figure 7.12 DTC Operation Timing (Chain Transfer).......................................................... 182
Section 8 I/O Ports
Figure 8.1 Port 1 Pin Functions .......................................................................................... 196
Figure 8.2 Port 1 Pin Functions (Mode 1) .......................................................................... 199
Figure 8.3 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 1)) ........................................... 199
Figure 8.4 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 0)) ........................................... 200
Figure 8.5 Port 2 Pin Functions .......................................................................................... 202
Figure 8.6 Port 2 Pin Functions (Mode 1) .......................................................................... 205
Figure 8.7 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 1)) ........................................... 206
Figure 8.8 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 0)) ........................................... 206
Figure 8.9 Port 3 Pin Functions .......................................................................................... 208
Figure 8.10 Port 3 Pin Functions (Modes 1, 2, and 3 (EXPE = 1)) ...................................... 211
Figure 8.11 Port 3 Pin Functions (Modes 2 and 3 (EXPE = 0)) ........................................... 211
Figure 8.12 Port 4 Pin Functions .......................................................................................... 213
Figure 8.13 Port 5 Pin Functions .......................................................................................... 218
Figure 8.14 Port 6 Pin Functions .......................................................................................... 221
Figure 8.15 Port 7 Pin Functions .......................................................................................... 228
Figure 8.16 Port 8 Pin Functions .......................................................................................... 230
Figure 8.17 Port 9 Pin Functions .......................................................................................... 234
Section 9 8-Bit PWM Timers [H8S/2138 Group]
Figure 9.1 Block Diagram of PWM Timer Module............................................................ 242
Figure 9.2 Example of Additional Pulse Timing
(When Upper 4 Bits of PWDR = 1000)............................................................. 252
Section 10 14-Bit PWM D/A
Figure 10.1 PWM D/A Block Diagram ................................................................................ 254
Figure 10.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT)..................................... 263
Figure 10.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT) ................................. 264
Figure 10.3 PWM D/A Operation......................................................................................... 265
Figure 10.4 (1) Output Waveform.............................................................................................. 267
Figure 10.4 (2) Output Waveform.............................................................................................. 267