Datasheet

Section 12 8-Bit Timers
Rev. 4.00 Jun 06, 2006 page 320 of 1004
REJ09B0301-0400
12.2.7 System Control Register (SYSCR)
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections
3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
Bit 1—Host Interface Enable (HIE): Controls CPU access to 8-bit timer (channel X and Y) data
registers and control registers, and timer connection control registers.
Bit 1
HIE Description
0 CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is enabled (Initial value)
1 CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is disabled
12.2.8 Timer Connection Register S (TCONRS)
7
TMRX/Y
0
R/W
6
ISGENE
0
R/W
5
HOMOD1
0
R/W
4
HOMOD0
0
R/W
3
VOMOD1
0
R/W
0
CLMOD0
0
R/W
2
VOMOD0
0
R/W
1
CLMOD1
0
R/W
Bit
Initial value
Read/Write
TCONRS is an 8-bit readable/writable register that controls access to the TMRX and TMRY
registers and timer connection operation.
TCONRS is initialized to H'00 by a reset and in hardware standby mode.