Datasheet

Section 12 8-Bit Timers
Rev. 4.00 Jun 06, 2006 page 314 of 1004
REJ09B0301-0400
TCR STCR
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 0 — — Clock input disabled (Initial value)
001—0 φ/8 internal clock source, counted on the falling edge
001—1 φ/2 internal clock source, counted on the falling edge
010—0 φ/64 internal clock source, counted on the falling edge
010—1 φ/32 internal clock source, counted on the falling edge
011—0 φ/1024 internal clock source, counted on the falling edge
011—1 φ/256 internal clock source, counted on the falling edge
1 0 0 — — Counted on TCNT1 overflow signal
*
1 0 0 0 — — Clock input disabled (Initial value)
0010 —φ/8 internal clock source, counted on the falling edge
0011 —φ/2 internal clock source, counted on the falling edge
0100 —φ/64 internal clock source, counted on the falling edge
0101 —φ/128 internal clock source, counted on the falling edge
0110 —φ/1024 internal clock source, counted on the falling edge
0111 —φ/2048 internal clock source, counted on the falling edge
1 0 0 — — Counted on TCNT0 compare-match A
*
X 0 0 0 — — Clock input disabled (Initial value)
0 0 1 — — Counted on φ internal clock source
010——φ/2 internal clock source, counted on the falling edge
011——φ/4 internal clock source, counted on the falling edge
1 0 0 — — Clock input disabled
Y 0 0 0 — — Clock input disabled (Initial value)
001——φ/4 internal clock source, counted on the falling edge
010——φ/256 internal clock source, counted on the falling edge
011——φ/2048 internal clock source, counted on the falling edge
1 0 0 — — Clock input disabled
Common 1 0 1 — — External clock source, counted at rising edge
1 1 0 — — External clock source, counted at falling edge
1 1 1 — — External clock source, counted at both rising and falling
edges
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0
compare-match signal, no incrementing clock will be generated. Do not use this setting.