Datasheet

Rev. 4.00 Jun 06, 2006 page xxxv of liv
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8S/2138 Group..................................................... 7
Figure 1.2 Internal Block Diagram of H8S/2134 Group..................................................... 8
Figure 1.3 Pin Arrangement of H8S/2138 Group (FP-80A, TFP-80C: Top View)............ 9
Figure 1.4 Pin Arrangement of H8S/2134 Group (FP-80A, TFP-80C: Top View)............ 10
Section 2 CPU
Figure 2.1 CPU Operating Modes....................................................................................... 28
Figure 2.2 Exception Vector Table (Normal Mode)........................................................... 29
Figure 2.3 Stack Structure in Normal Mode....................................................................... 30
Figure 2.4 Exception Vector Table (Advanced Mode)....................................................... 31
Figure 2.5 Stack Structure in Advanced Mode................................................................... 32
Figure 2.6 Memory Map..................................................................................................... 33
Figure 2.7 CPU Registers ................................................................................................... 34
Figure 2.8 Usage of General Registers ............................................................................... 35
Figure 2.9 Stack .................................................................................................................. 36
Figure 2.10 General Register Data Formats.......................................................................... 39
Figure 2.11 Memory Data Formats....................................................................................... 41
Figure 2.12 Instruction Formats (Examples) ........................................................................ 54
Figure 2.13 Branch Address Specification in Memory Indirect Mode ................................. 57
Figure 2.14 Processing States ............................................................................................... 62
Figure 2.15 State Transitions................................................................................................ 63
Figure 2.16 Stack Structure after Exception Handling (Examples)...................................... 65
Figure 2.17 On-Chip Memory Access Cycle........................................................................ 67
Figure 2.18 Pin States during On-Chip Memory Access...................................................... 67
Figure 2.19 On-Chip Supporting Module Access Cycle....................................................... 68
Figure 2.20 Pin States during On-Chip Supporting Module Access..................................... 69
Section 3 MCU Operating Modes
Figure 3.1 H8S/2138 (Except for F-ZTAT A-Mask Version) and H8S/2134 Memory Map
in Each Operating Mode.................................................................................... 80
Figure 3.2 H8S/2138 F-ZTAT A-Mask Version Memory Map in Each Operating Mode 82
Figure 3.3 H8S/2133 Memory Map in Each Operating Mode............................................ 84
Figure 3.4 H8S/2137 and H8S/2132 Memory Map in Each Operating Mode.................... 86
Figure 3.5 H8S/2130 Memory Map in Each Operating Mode............................................ 88
Section 4 Exception Handling
Figure 4.1 Exception Sources ............................................................................................. 92