Datasheet

Section 12 8-Bit Timers
Rev. 4.00 Jun 06, 2006 page 312 of 1004
REJ09B0301-0400
12.2.4 Timer Control Register (TCR)
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
TCR is an 8-bit readable/writable register that selects the clock source and the time at which
TCNT is cleared, and enables interrupts.
TCR is initialized to H'00 by a reset and in hardware standby mode.
For details of the timing, see section 12.3, Operation.
Bit 7—Compare-Match Interrupt Enable B (CMIEB): Selects whether the CMFB interrupt
request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Note that a CMIB interrupt is not requested by TMRX, regardless of the CMIEB value.
Bit 7
CMIEB Description
0 CMFB interrupt request (CMIB) is disabled (Initial value)
1 CMFB interrupt request (CMIB) is enabled
Bit 6—Compare-Match Interrupt Enable A (CMIEA): Selects whether the CMFA interrupt
request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1.
Note that a CMIA interrupt is not requested by TMRX, regardless of the CMIEA value.
Bit 6
CMIEA Description
0 CMFA interrupt request (CMIA) is disabled (Initial value)
1 CMFA interrupt request (CMIA) is enabled