Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 301 of 1004
REJ09B0301-0400
φ
Address
OCRAR (OCRAF) address
Internal write
signal
Compare-match
signal
FRC
Inhibited
OCRA N
N N + 1
OCRAR
(OCRAF)
Old Data New Data
The compare-match signal is inhibited and
automatic addition does not occur.
Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function Is Used)