Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 300 of 1004
REJ09B0301-0400
Contention between OCR Write and Compare-Match: If a compare-match occurs during the
state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal
is inhibited.
Figure 11.20 shows this type of contention.
If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in
the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of
the automatic addition is not written to OCRA.
Figure 11.21 shows this type of contention.
T
1
T
2
OCRA or OCRB write cycle
Address
Internal write signal
φ
FRC
OCR N M
Write data
OCR address
N N + 1
Compare-match
signal
Inhibited
Figure 11.20 Contention between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used)