Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 299 of 1004
REJ09B0301-0400
Contention between FRC Write and Increment: If an FRC increment pulse is generated during
the state after an FRC write cycle, the write takes priority and FRC is not incremented.
Figure 11.19 shows this type of contention.
T
1
T
2
FRC write cycle
Address
Internal write signal
φ
FRC input clock
FRC N M
Write data
FRC address
Figure 11.19 FRC Write-Increment Contention