Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 289 of 1004
REJ09B0301-0400
11.3.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
N H'0000
FRC
φ
Compare-match A
signal
Figure 11.6 Clearing of FRC by Compare-Match A
11.3.4 Input Capture Input Timing
Input Capture Input Timing: An internal input capture signal is generated from the rising or
falling edge of the signal at the input capture pin, as selected by the corresponding IEDGx (x = A
to D) bit in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is
selected (IEDGx = 1).
Input capture
signal
φ
Input capture
input pin
Figure 11.7 Input Capture Signal Timing (Usual Case)
If the upper byte of ICRA to ICRD is being read when the corresponding input capture signal
arrives, the internal input capture signal is delayed by one system clock (φ) period. Figure 11.8
shows the timing for this case.