Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 287 of 1004
REJ09B0301-0400
11.3 Operation
11.3.1 FRC Increment Timing
FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source.
Internal Clock: Any of three internal clocks (φ/2, φ/8, or φ/32) created by division of the system
clock (φ) can be selected by making the appropriate setting in bits CKS1 and CKS0 in TCR.
Figure 11.3 shows the increment timing.
N – 1
FRC input
clock
φ
FRC
Internal
clock
N N + 1
Figure 11.3 Increment Timing with Internal Clock Source
External Clock: If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC
increments on the rising edge of the external clock signal.
The pulse width of the external clock signal must be at least 1.5 system clock (φ) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
Figure 11.4 shows the increment timing.