Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 285 of 1004
REJ09B0301-0400
Bit 5
ICRS Description
0 The ICRA, ICRB, and ICRC registers are selected (Initial value)
1 The OCRAR, OCRAF, and OCRDM registers are selected
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4
OCRS Description
0 The OCRA register is selected (Initial value)
1 The OCRB register is selected
Bit 3—Output Enable A (OEA): Enables or disables output of the output compare A signal
(FTOA).
Bit 3
OEA Description
0 Output compare A output is disabled (Initial value)
1 Output compare A output is enabled
Bit 2—Output Enable B (OEB): Enables or disables output of the output compare B signal
(FTOB).
Bit 2
OEB Description
0 Output compare B output is disabled (Initial value)
1 Output compare B output is enabled
Bit 1—Output Level A (OLVLA): Selects the logic level to be output at the FTOA pin in
response to compare-match A (signal indicating a match between the FRC and OCRA values).
When the OCRAMS bit is 1, this bit is ignored.