Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 284 of 1004
REJ09B0301-0400
11.2.9 Timer Output Compare Control Register (TOCR)
Bit
Initial value
Read/Write
7
ICRDMS
0
R/W
6
OCRAMS
0
R/W
5
ICRS
0
R/W
4
OCRS
0
3
OEA
0
0
OLVLB
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
R/W
R/W
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, switches access between output compare registers A and B, controls the
ICRD and OCRA operating mode, and switches access to input capture registers A, B, and C.
TOCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Input Capture D Mode Select (ICRDMS): Specifies whether ICRD is used in the normal
operating mode or in the operating mode using OCRDM.
Bit 7
ICRDMS Description
0 The normal operating mode is specified for ICRD (Initial value)
1 The operating mode using OCRDM is specified for ICRD
Bit 6—Output Compare A Mode Select (OCRAMS): Specifies whether OCRA is used in the
normal operating mode or in the operating mode using OCRAR and OCRAF.
Bit 6
OCRAMS Description
0 The normal operating mode is specified for OCRA (Initial value)
1 The operating mode using OCRAR and OCRAF is specified for OCRA
Bit 5—Input Capture Register Select (ICRS): The same addresses are shared by ICRA and
OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which
registers are selected when the shared addresses are read or written to. The operation of ICRA,
ICRB, and ICRC is not affected.