Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 282 of 1004
REJ09B0301-0400
11.2.8 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
Bit 7
IEDGA Description
0 Capture on the falling edge of FTIA (Initial value)
1 Capture on the rising edge of FTIA
Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B
signal (FTIB).
Bit 6
IEDGB Description
0 Capture on the falling edge of FTIB (Initial value)
1 Capture on the rising edge of FTIB
Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C
signal (FTIC).
Bit 5
IEDGC Description
0 Capture on the falling edge of FTIC (Initial value)
1 Capture on the rising edge of FTIC