Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Jun 06, 2006 page 278 of 1004
REJ09B0301-0400
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output
compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3
OCIAE Description
0 Output compare interrupt request A (OCIA) is disabled (Initial value)
1 Output compare interrupt request A (OCIA) is enabled
Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output
compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 2
OCIBE Description
0 Output compare interrupt request B (OCIB) is disabled (Initial value)
1 Output compare interrupt request B (OCIB) is enabled
Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running
timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit 1
OVIE Description
0 Timer overflow interrupt request (FOVI) is disabled (Initial value)
1 Timer overflow interrupt request (FOVI) is enabled
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
11.2.7 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)
*
6
ICFB
0
R/(W)
*
5
ICFC
0
4
ICFD
0
3
OCFA
0
0
CCLRA
0
R/W
2
OCFB
0
R/(W)
*
1
OVF
0
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
Note: * Only 0 can be written in bits 7 to 1 to clear these flags.
TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals.
TCSR is initialized to H'00 by a reset and in hardware standby mode.