Datasheet

Section 10 14-Bit PWM D/A
Rev. 4.00 Jun 06, 2006 page 267 of 1004
REJ09B0301-0400
1. OS = 0 (DADR corresponds to T
L
)
a. CFS = 0 [base cycle = resolution (T) × 64]
t
L1
t
L2
t
L3
t
L255
t
L256
t
f1
t
f2
t
f255
t
f256
1 conversion cycle
t
f1
= t
f2
= t
f3
= · · · = t
f255
= t
f256
= T × 64
t
L1
+ t
L2
+ t
L3
+ · · · + t
L255
+ t
L256
= T
L
Figure 10.4 (1) Output Waveform
b. CFS = 1 [base cycle = resolution (T) × 256]
t
L1
t
L2
t
L3
t
L63
t
L64
t
f1
t
f2
t
f63
t
f64
1 conversion cycle
t
f1
= t
f2
= t
f3
= · · · = t
f63
= t
f64
= T × 256
t
L1
+ t
L2
+ t
L3
+ · · · + t
L63
+ t
L64
= T
L
Figure 10.4 (2) Output Waveform