Datasheet

Section 10 14-Bit PWM D/A
Rev. 4.00 Jun 06, 2006 page 260 of 1004
REJ09B0301-0400
Bit 2—Output Enable A (OEA): Enables or disables output on PWM D/A channel A.
Bit 2
OEA Description
0 PWM (D/A) channel A output (at the PWX0 pin) is disabled (Initial value)
1 PWM (D/A) channel A output (at the PWX0 pin) is enabled
Bit 1—Output Select (OS): Selects the phase of the PWM D/A output.
Bit 1
OS Description
0 Direct PWM output (Initial value)
1 Inverted PWM output
Bit 0—Clock Select (CKS): Selects the PWM D/A resolution. If the system clock (φ) frequency
is 10 MHz, resolutions of 100 ns and 200 ns can be selected.
Bit 0
CKS Description
0 Operates at resolution (T) = system clock cycle time (t
cyc
) (Initial value)
1 Operates at resolution (T) = system clock cycle time (t
cyc
) × 2