Datasheet

Section 10 14-Bit PWM D/A
Rev. 4.00 Jun 06, 2006 page 257 of 1004
REJ09B0301-0400
10.2.2 D/A Data Registers A and B (DADRA and DADRB)
15
13
DA13
1
R/W
14
12
DA12
1
R/W
13
11
DA11
1
R/W
12
10
DA10
1
R/W
11
9
DA9
1
R/W
8
6
DA6
1
R/W
10
8
DA8
1
R/W
9
7
DA7
1
R/W
Bit (CPU)
Bit (Data)
DADRA
Initial value
Read/Write
7
5
DA5
1
R/W
6
4
DA4
1
R/W
5
3
DA3
1
R/W
4
2
DA2
1
R/W
3
1
DA1
1
R/W
0
—
—
1
—
2
0
DA0
1
R/W
1
—
CFS
1
R/W
DADRH
DADRL
DA13
1
R/W
DA12
1
R/W
DA11
1
R/W
DA10
1
R/W
DA9
1
R/W
DA6
1
R/W
DA8
1
R/W
DA7
1
R/W
DADRB
Initial value
Read/Write
DA5
1
R/W
DA4
1
R/W
DA3
1
R/W
DA2
1
R/W
DA1
1
R/W
REGS
1
R/W
DA0
1
R/W
CFS
1
R/W
There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA
corresponds to PWM D/A channel A, and DADRB to PWM D/A channel B. The CPU can read
and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers,
data transfers between them and the CPU are performed using a temporary register (TEMP). See
section 10.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is not used and is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.