Datasheet

Section 8 I/O Ports
Rev. 4.00 Jun 06, 2006 page 236 of 1004
REJ09B0301-0400
• Modes 2 and 3 (EXPE = 0)
When the corresponding P9DDR bits are set to 1, pin P96 functions as the φ output pin and
pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the
corresponding pins become input ports.
Port 9 Data Register (P9DR)
Bit 76543210
P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR
Initial value 0 —
*
000000
Read/Write R/W R R/W R/W R/W R/W R/W R/W
Note: * Determined by the state of pin P96.
P9DR is an 8-bit readable/writable register that stores output data for the port 9 pins (P97 to P90).
With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR
values are read directly, regardless of the actual pin states. If a port 9 read is performed while
P9DDR bits are cleared to 0, the pin states are read.
P9DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.10.3 Pin Functions
Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter trigger
input pin (ADTRG), HIF input pins (ECS2, CS1, IOW, IOR), the IIC0 I/O pin (SDA0), the
subclock input pin (EXCL), bus control signal I/O pins (AS/IOS, RD, WR, WAIT), and the
system clock (φ) output pin. The pin functions differ between the mode 1, 2, and 3 (EXPE = 1)
expanded modes and the mode 2 and 3 (EXPE = 0) single-chip modes. The port 9 pin functions
are shown in table 8.20.