Datasheet

Section 8 I/O Ports
Rev. 4.00 Jun 06, 2006 page 216 of 1004
REJ09B0301-0400
Pin Selection Method and Pin Functions
P43/TMCI1/
HIRQ11/HSYNCI
The pin function is switched as shown below according to the combination of
the operating mode and bit P43DDR.
P43DDR 0 1
Operating
mode
— Not slave mode Slave mode
Pin function P43 input pin P43 output pin HIRQ11 output pin
TMCI1 input pin, HSYNCI input pin
When an external clock is selected with bits CKS2 to CKS0 in TCR1 of TMR1,
this pin is used as the TMCI1 input pin. It can also be used as the HSYNCI
input pin.
P42/TMRI0/
SCK2/SDA1
The pin function is switched as shown below according to the combination of
bit ICE in ICCR of IIC1, bits CKE1 and CKE0 in SCR of SCI2, bit C/A in SMR
of SCI2, and bit P42DDR.
ICE 0 1
CKE1 0 1 0
C/A 01— 0
CKE0 0 1 —— 0
P42DDR 0 1 ————
Pin function P42
input pin
P42
output pin
SCK2
output pin
SCK2
output pin
SCK2
input pin
SDA1
I/O pin
TMRI0 input pin
When this pin is used as the SDA1 I/O pin, bits CKE1 and CKE0 in SCR of
SCI2 and bit C/A in SMR of SCI2 must all be cleared to 0. SDA1 is an NMOS-
only output, and has direct bus drive capability.
When bits CCLR1 and CCLR0 in TCR0 of TMR0 are set to 1, this pin is used
as the TMRI0 input pin.