Datasheet

Section 8 I/O Ports
Rev. 4.00 Jun 06, 2006 page 209 of 1004
REJ09B0301-0400
8.4.2 Register Configuration
Table 8.7 shows the port 3 register configuration.
Table 8.7 Port 3 Registers
Name Abbreviation R/W Initial Value Address
*
Port 3 data direction register P3DDR W H'00 H'FFB4
Port 3 data register P3DR R/W H'00 H'FFB6
Port 3 MOS pull-up control
register
P3PCR R/W H'00 H'FFAE
Note: * Lower 16 bits of the address.
Port 3 Data Direction Register (P3DDR)
7
P37DDR
0
W
6
P36DDR
0
W
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
0
P30DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
Bit
Initial value
Read/Write
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 1, 2, and 3 (EXPE = 1)
The input/output direction specified by P3DDR is ignored, and pins automatically function as
data I/O pins.
After a reset, and in hardware standby mode or software standby mode, the data I/O pins go to
the high-impedance state.
• Modes 2 and 3 (EXPE = 0)
The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports
when cleared to 0.