Datasheet

Rev. 4.00 Jun 06, 2006 page xx of liv
6.1.1 Features................................................................................................................ 137
6.1.2 Block Diagram..................................................................................................... 138
6.1.3 Pin Configuration................................................................................................. 139
6.1.4 Register Configuration......................................................................................... 139
6.2 Register Descriptions........................................................................................................ 140
6.2.1 Bus Control Register (BCR) ................................................................................ 140
6.2.2 Wait State Control Register (WSCR) .................................................................. 141
6.3 Overview of Bus Control.................................................................................................. 143
6.3.1 Bus Specifications................................................................................................ 143
6.3.2 Advanced Mode................................................................................................... 144
6.3.3 Normal Mode....................................................................................................... 144
6.3.4 I/O Select Signal .................................................................................................. 145
6.4 Basic Bus Interface ........................................................................................................... 146
6.4.1 Overview.............................................................................................................. 146
6.4.2 Data Size and Data Alignment............................................................................. 146
6.4.3 Valid Strobes........................................................................................................ 147
6.4.4 Basic Timing........................................................................................................ 148
6.4.5 Wait Control ........................................................................................................ 151
6.5 Burst ROM Interface......................................................................................................... 153
6.5.1 Overview.............................................................................................................. 153
6.5.2 Basic Timing........................................................................................................ 153
6.5.3 Wait Control ........................................................................................................ 155
6.6 Idle Cycle.......................................................................................................................... 155
6.6.1 Operation ............................................................................................................. 155
6.6.2 Pin States in Idle Cycle........................................................................................ 156
6.7 Bus Arbitration.................................................................................................................. 157
6.7.1 Overview.............................................................................................................. 157
6.7.2 Operation ............................................................................................................. 157
6.7.3 Bus Transfer Timing............................................................................................ 158
Section 7 Data Transfer Controller [H8S/2138 Group]............................................ 159
7.1 Overview........................................................................................................................... 159
7.1.1 Features................................................................................................................ 159
7.1.2 Block Diagram..................................................................................................... 160
7.1.3 Register Configuration......................................................................................... 161
7.2 Register Descriptions........................................................................................................ 162
7.2.1 DTC Mode Register A (MRA) ............................................................................ 162
7.2.2 DTC Mode Register B (MRB)............................................................................. 164
7.2.3 DTC Source Address Register (SAR).................................................................. 165
7.2.4 DTC Destination Address Register (DAR).......................................................... 165
7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 165