Datasheet

Section 6 Bus Controller
Rev. 4.00 Jun 06, 2006 page 156 of 1004
REJ09B0301-0400
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output
floating time
Data collision
(a) Idle cycle not inserted
T
1
φ
RD
T
2
T
3
T
I
T
1
(b) Idle cycle inserted
T
2
WR
WR
Address bus
Data bus
Bus cycle A Bus cycle B
Figure 6.9 Example of Idle Cycle Operation
6.6.2 Pin States in Idle Cycle
Table 6.6 shows pin states in an idle cycle.
Table 6.6 Pin States in Idle Cycle
Pins Pin State
A15 to A0, IOS Contents of next bus cycle
D7 to D0 High impedance
AS High
RD High
WR High