Datasheet

Section 6 Bus Controller
Rev. 4.00 Jun 06, 2006 page 154 of 1004
REJ09B0301-0400
T
1
Address bus
φ
A
S
/
IOS
(IOSE = 0)
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 6.8 (a) Example of Burst ROM Access Timing (When AST = BRSTS1 = 1)
T
1
Address bus
φ
A
S/IOS (IOSE = 0)
Data bus
T
2
T
1
T
1
Full access
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 6.8 (b) Example of Burst ROM Access Timing (When AST = BRSTS1 = 0)