Datasheet

Rev. 4.00 Jun 06, 2006 page xix of liv
Section 5 Interrupt Controller .......................................................................................... 101
5.1 Overview........................................................................................................................... 101
5.1.1 Features................................................................................................................ 101
5.1.2 Block Diagram..................................................................................................... 102
5.1.3 Pin Configuration................................................................................................. 102
5.1.4 Register Configuration......................................................................................... 103
5.2 Register Descriptions........................................................................................................ 104
5.2.1 System Control Register (SYSCR)...................................................................... 104
5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 105
5.2.3 IRQ Enable Register (IER) .................................................................................. 106
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 106
5.2.5 IRQ Status Register (ISR).................................................................................... 107
5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) ......................................... 109
5.2.7 Address Break Control Register (ABRKCR)....................................................... 111
5.2.8 Break Address Registers A, B, C (BARA, BARB, BARC)................................. 112
5.3 Interrupt Sources............................................................................................................... 113
5.3.1 External Interrupts ............................................................................................... 113
5.3.2 Internal Interrupts................................................................................................. 115
5.3.3 Interrupt Exception Vector Table ........................................................................ 115
5.4 Address Breaks ................................................................................................................. 118
5.4.1 Features................................................................................................................ 118
5.4.2 Block Diagram..................................................................................................... 118
5.4.3 Operation ............................................................................................................. 119
5.4.4 Usage Notes ......................................................................................................... 119
5.5 Interrupt Operation............................................................................................................ 121
5.5.1 Interrupt Control Modes and Interrupt Operation................................................ 121
5.5.2 Interrupt Control Mode 0..................................................................................... 124
5.5.3 Interrupt Control Mode 1..................................................................................... 126
5.5.4 Interrupt Exception Handling Sequence .............................................................. 129
5.5.5 Interrupt Response Times .................................................................................... 131
5.6 Usage Notes ...................................................................................................................... 132
5.6.1 Contention between Interrupt Generation and Disabling..................................... 132
5.6.2 Instructions that Disable Interrupts...................................................................... 133
5.6.3 Interrupts during Execution of EEPMOV Instruction.......................................... 133
5.7 DTC Activation by Interrupt............................................................................................. 134
5.7.1 Overview.............................................................................................................. 134
5.7.2 Block Diagram..................................................................................................... 134
5.7.3 Operation ............................................................................................................. 135
Section 6 Bus Controller ................................................................................................... 137
6.1 Overview........................................................................................................................... 137