Datasheet

Section 6 Bus Controller
Rev. 4.00 Jun 06, 2006 page 150 of 1004
REJ09B0301-0400
8-Bit 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
Wait states can be inserted.
These group have no lower data bus (D7 to D0) pins or LWR pin. In these group, the upper data
bus (D15 to D8) pins are designated D7 to D0, and the HWR signal pin is designated WR.
Bus cycle
T
1
T
2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
D15 to D8
Valid
Write
T
3
Figure 6.6 Bus Timing for 8-Bit 3-State Access Space