Datasheet

Section 6 Bus Controller
Rev. 4.00 Jun 06, 2006 page 148 of 1004
REJ09B0301-0400
Table 6.5 Data Buses Used and Valid Strobes
Area
Access
Size
Read/
Write Address
Valid
Strobe
Upper Data Bus
(D15 to D8)
*
1
Lower Data Bus
(D7 to D0)
*
3
Byte Read — RD Valid Port, etc.8-bit access
space
Write — HWR
*
2
Port, etc.
Byte Read Even RD Valid Invalid
Odd Invalid Valid
Write Even HWR Valid Undefined
Odd LWR Undefined Valid
Word Read — RD Valid Valid
16-bit access
space (Cannot
be used in the
H8S/2138 Group
or H8S/2134
Group)
Write — HWR,
LWR
Valid Valid
Notes: Undefined: Undefined data is output.
Invalid: Input state; input value is ignored.
Port, etc.: Pins are used as port or on-chip supporting module input/output pins, and not as
data bus pins.
1. The pin names in these group are D7 to D0.
2. The pin name in these group is WR.
3. There are no lower data bus pins in these group.
6.4.4 Basic Timing
8-Bit 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
Wait states cannot be inserted.
These group have no lower data bus (D7 to D0) pins or LWR pin. In these group, the upper data
bus (D15 to D8) pins are designated D7 to D0, and the HWR signal pin is designated WR.