Datasheet

Section 6 Bus Controller
Rev. 4.00 Jun 06, 2006 page 147 of 1004
REJ09B0301-0400
16-Bit Access Space (Cannot Be Used in the H8S/2138 Group or H8S/2134 Group): Figure
6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the
upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of
data that can be accessed at one time is one byte or one word, and a longword access is executed
as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
D15 D8 D7 D0
Upper data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
• Even address
Byte size • Odd address
Lower data bus
Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space)
6.4.3 Valid Strobes
Table 6.5 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
These group only have an upper data bus, and only the RD and HWR signals are valid. In these
group, the HWR signal pin is designated WR.