Datasheet

Section 6 Bus Controller
Rev. 4.00 Jun 06, 2006 page 144 of 1004
REJ09B0301-0400
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
Bus Specifications (Basic Bus Interface)
ABW AST WMS1 WMS0 WC1 WC0 Bus Width
Access
States
Program
Wait States
00———— Cannot be used in the H8S/2138 Group or
H8S/2134 Group.
10———— 820
101—— 830
—* —* 00 3 0
11
10 2
13
Note: * Except when WMS1 = 0 and WMS0 = 1
6.3.2 Advanced Mode
The H8S/2138 and H8S/2134 have 16 address output pins, so there are no pins for output of the
upper address bits (A16 to A23) in advanced mode. H'FFF000 to H'FFFE4F (H'FFF000 to
H'FFF7FF in the H8S/2138 F-ZTAT A mask version) can be accessed by designating the AS pin
as an I/O strobe pin. The accessible external space is therefore H'FFF000 to H'FFFE4F (H'FFF000
to H'FFF7FF in the H8S/2138 F-ZTAT A mask version) even when expanded mode with ROM
enabled is selected in advanced mode.
The initial state of the external space is basic bus interface, three-state access space. In ROM-
enabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O
registers is external space. The on-chip RAM is enabled when the RAME bit in the system control
register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and
the corresponding space becomes external space.
6.3.3 Normal Mode
The initial state of the external memory space is basic bus interface, three-state access space. In
ROM-disabled expanded mode, the space excluding the on-chip RAM and internal I/O registers is
external space. In ROM-enabled expanded mode, the space excluding the on-chip ROM, on-chip
RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME
bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-
chip RAM is disabled and the corresponding space becomes external space.