Datasheet

Rev. 4.00 Jun 06, 2006 page xviii of liv
2.8.5 Bus-Released State............................................................................................... 65
2.8.6 Power-Down State ............................................................................................... 65
2.9 Basic Timing..................................................................................................................... 66
2.9.1 Overview.............................................................................................................. 66
2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 66
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 68
2.9.4 External Address Space Access Timing .............................................................. 69
2.10 Usage Note........................................................................................................................ 70
2.10.1 TAS Instruction.................................................................................................... 70
2.10.2 STM/LDM Instruction......................................................................................... 70
Section 3 MCU Operating Modes .................................................................................. 71
3.1 Overview........................................................................................................................... 71
3.1.1 Operating Mode Selection ................................................................................... 71
3.1.2 Register Configuration......................................................................................... 72
3.2 Register Descriptions........................................................................................................72
3.2.1 Mode Control Register (MDCR) ......................................................................... 72
3.2.2 System Control Register (SYSCR)...................................................................... 73
3.2.3 Bus Control Register (BCR) ................................................................................ 75
3.2.4 Serial Timer Control Register (STCR) ................................................................ 76
3.3 Operating Mode Descriptions........................................................................................... 78
3.3.1 Mode 1................................................................................................................. 78
3.3.2 Mode 2................................................................................................................. 78
3.3.3 Mode 3................................................................................................................. 78
3.4 Pin Functions in Each Operating Mode ............................................................................ 79
3.5 Memory Map in Each Operating Mode ............................................................................ 79
Section 4 Exception Handling ......................................................................................... 91
4.1 Overview........................................................................................................................... 91
4.1.1 Exception Handling Types and Priority............................................................... 91
4.1.2 Exception Handling Operation............................................................................. 92
4.1.3 Exception Sources and Vector Table................................................................... 92
4.2 Reset.................................................................................................................................. 94
4.2.1 Overview.............................................................................................................. 94
4.2.2 Reset Sequence .................................................................................................... 94
4.2.3 Interrupts after Reset............................................................................................ 96
4.3 Interrupts........................................................................................................................... 97
4.4 Trap Instruction................................................................................................................. 98
4.5 Stack Status after Exception Handling.............................................................................. 99
4.6 Notes on Use of the Stack................................................................................................. 100