Datasheet

Section 6 Bus Controller
Rev. 4.00 Jun 06, 2006 page 141 of 1004
REJ09B0301-0400
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1 Description
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 states (Initial value)
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0 Description
0 Max. 4 words in burst access (Initial value)
1 Max. 8 words in burst access
Bit 2—Reserved: Do not write 0 to this bit.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): See table 6.4.
6.2.2 Wait State Control Register (WSCR)
7
RAMS
0
R/W
6
RAM0
0
R/W
5
ABW
1
R/W
4
AST
1
R/W
3
WMS1
0
R/W
0
WC0
1
R/W
2
WMS0
0
R/W
1
WC1
1
R/W
Bit
Initial value
Read/Write
WSCR is an 8-bit readable/writable register that specifies the data bus width, number of access
states, wait mode, and number of wait states for external memory space. The on-chip memory and
internal I/O register bus width and number of access states are fixed, irrespective of the WSCR
settings.
WSCR is initialized to H'33 by a reset and in hardware standby mode. It is not initialized in
software standby mode.