Datasheet

Section 5 Interrupt Controller

Rev. 4.00 Jun 06, 2006 page 121 of 1004

REJ09B0301-0400

5.5 Interrupt Operation

5.5.1 Interrupt Control Modes and Interrupt Operation

Interrupt operations in the H8S/2138 Group and H8S/2134 Group differ depending on the

interrupt control mode.

NMI and address break interrupts are accepted at all times except in the reset state and the

hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an

enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding

interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the

interrupt controller.

Table 5.5 shows the interrupt control modes.

The interrupt controller performs interrupt control according to the interrupt control mode set by

the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated

by the I and UI bits in the CPU’s CCR.

Table 5.5 Interrupt Control Modes

SYSCR

Interrupt

Control Mode

INTM1 INTM0

Priority Setting

Interrupt

Mask Bits

Description

0 0 0 ICR I Interrupt mask control is

performed by the I bit

Priority can be set with ICR

1 1 ICR I, UI 3-level interrupt mask control

is performed by the I and UI

bits

Priority can be set with ICR