Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Jun 06, 2006 page 117 of 1004
REJ09B0301-0400
Vector Address
Interrupt Source
Origin of
Interrupt
Source
Vector
Number
Normal
Mode
Advanced
Mode ICR Priority
CMIA0 (compare-match A)
CMIB0 (compare-match B)
OVI0 (overflow)
Reserved
8-bit timer
channel 0
64
65
66
67
H'0080
H'0082
H'0084
H'0086
H'000100
H'000104
H'000108
H'00010C
ICRB3 High
CMIA1 (compare-match A)
CMIB1 (compare-match B)
OVI1 (overflow)
Reserved
8-bit timer
channel 1
68
69
70
71
H'0088
H'008A
H'008C
H'008E
H'000110
H'000114
H'000118
H'00011C
ICRB2
CMIAY (compare-match A)
CMIBY (compare-match B)
OVIY (overflow)
ICIX (input capture X)
8-bit timer
channels
Y, X
72
73
74
75
H'0090
H'0092
H'0094
H'0096
H'000120
H'000124
H'000128
H'00012C
ICRB1
IBF1 (IDR1 reception completed)
IBF2 (IDR2 reception completed)
Reserved
Reserved
Host
interface
76
77
78
79
H'0098
H'009A
H'009C
H'009E
H'000130
H'000134
H'000138
H'00013C
ICRB0
ERI0 (receive error 0)
RXI0 (reception completed 0)
TXI0 (transmit data empty 0)
TEI0 (transmission end 0)
SCI
channel 0
80
81
82
83
H'00A0
H'00A2
H'00A4
H'00A6
H'000140
H'000144
H'000148
H'00014C
ICRC7
ERI1 (receive error 1)
RXI1 (reception completed 1)
TXI1 (transmit data empty 1)
TEI1 (transmission end 1)
SCI
channel 1
84
85
86
87
H'00A8
H'00AA
H'00AC
H'00AE
H'000150
H'000154
H'000158
H'00015C
ICRC6
ERI2 (receive error 2)
RXI2 (reception completed 2)
TXI2 (transmit data empty 2)
TEI2 (transmission end 2)
SCI
channel 2
88
89
90
91
H'00B0
H'00B2
H'00B4
H'00B6
H'000160
H'000164
H'000168
H'00016C
ICRC5
IICI0 (1-byte transmission/
reception completed)
DDCSWI (format switch)
IIC
channel 0
(option)
92
93
H'00B8
H'00BA
H'000170
H'000174
ICRC4
IICI1 (1-byte transmission/
reception completed)
Reserved
IIC
channel 1
(option)
94
95
H'00BC
H'00BE
H'000178
H'00017C
ICRC3
Reserved — 96
to
103
H'00C0
to
H'00CE
H'000180
to
H'00019C Low