Datasheet

Rev. 4.00 Jun 06, 2006 page xv of liv
Item Page Revision (See Manual for Details)
B.3 Function 942 WSCR H'FFC7 Bus Controller
Figure amended
7
RAMS
0
R/W
6
RAM0
0
R/W
Bit
Initial value
Read/Write
Reserved
Note: Always write 0
when writing to
these bits in
the A-mask
version.
959 STR1, 2 H'FFF6, H'FFFE HIF
Figure amended
0
OBF
0
R/(W)
R
1
IBF
0
R
R
Bit
Initial value
Slave R/W
Host R/W
Output data register full
0 [Clearing condition]
When the host processor
reads ODR or the slave
writes 0 in the OBF bit
1 [Setting condition]
When the slave processor
writes to ODR
Input data register full
0 [Clearing condition]
When the slave processor reads IDR
1 [Setting condition]
When the host processor writes to IDR