Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Jun 06, 2006 page 112 of 1004
REJ09B0301-0400
5.2.8 Break Address Registers A, B, C (BARA, BARB, BARC)
7
A23
0
R/W
6
A22
0
R/W
5
A21
0
R/W
4
A20
0
R/W
3
A19
0
R/W
0
A16
0
R/W
2
A18
0
R/W
1
A17
0
R/W
Bit
BARA
Initial value
Read/Write
7
A15
0
R/W
6
A14
0
R/W
5
A13
0
R/W
4
A12
0
R/W
3
A11
0
R/W
0
A8
0
R/W
2
A10
0
R/W
1
A9
0
R/W
Bit
BARB
Initial value
Read/Write
7
A7
0
R/W
6
A6
0
R/W
5
A5
0
R/W
4
A4
0
R/W
3
A3
0
R/W
0
—
0
—
2
A2
0
R/W
1
A1
0
R/W
Bit
BARC
Initial value
Read/Write
BAR consists of three 8-bit readable/writable registers (BARA, BARB, and BARC), and is used to
specify the address at which an address break is to be executed.
Each of the BAR registers is initialized to H'00 by a reset and in hardware standby mode. They are
not initialized in software standby mode.
BARA Bits 7 to 0—Address 23 to 16 (A23 to A16)
BARB Bits 7 to 0—Address 15 to 8 (A15 to A8)
BARC Bits 7 to 1—Address 7 to 1 (A7 to A1)
These bits specify the address at which an address break is to be executed. BAR bits A15 to A1
are compared with internal address bus lines A15 to A1, respectively.
The address at which the first instruction byte is located should be specified as the break address.
Occurrence of the address break condition may not be recognized for other addresses.
In normal mode, no comparison is made with address lines A23 to A16.
BARC Bit 0—Reserved: This bit cannot be modified and is always read as 0.