Datasheet

Rev. 4.00 Jun 06, 2006 page xiv of liv
Item Page Revision (See Manual for Details)
B.3 Function 938 STCR H'FFC3 System
Figure amended
7
—
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
ICKS0
0
R/W
2
—
0
R/W
1
ICKS1
0
R/W
Bit
Initial value
Read/Write
Internal Clock Source
Select 1 and 0
*
1
Reserved
Flash memory control register enable
0 Flash memory control register not selected
1 Flash memory control register selected
I
2
C master enable
0 CPU access to SCI0, SCI1, and SCI2 control
registers is enabled
1 CPU access to I
2
C bus interface data, PWMX data
registers and control registers is enabled
I
2
C transfer select 1 and 0
*
2
Reserved
939 SYSCR H'FFC4 System
Figure amended
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
RAM Enable
0
On-chip RAM is disabled
1 On-chip RAM is enabled
Host interface enable
0
Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to 8-bit timer (channel
X and Y) data registers and control
registers, and timer connection
control registers
1 Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to host interface data
registers and control registers, and
keyboard controller and MOS input
pull-up control registers
NMI edge select
0
Falling edge
1 Rising edge
External reset
0
Reset generated by watchdog timer overflow
1 Reset generated by an external reset
Interrupt control selection mode 1 and 0
INTM1
Bit 5
Interrupts controlled by I bit (Initial value)
Interrupts controlled by I and UI bits, and ICR
Cannot be used in the LSI
Cannot be used in the LSI
INTM0
Bit 4
Interrupt
control mode
Description
0
1
00
1
2
3
1
0
1