Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Jun 06, 2006 page 101 of 1004
REJ09B0301-0400
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
H8S/2138 Group and H8S/2134 Group MCUs control interrupts by means of an interrupt
controller. The interrupt controller has the following features:
• Two interrupt control modes
 Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
in the system control register (SYSCR).
• Priorities settable with ICR
 An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority
levels can be set for each module for all interrupts except NMI and address break.
• Independent vector addresses
 All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Fifteen external interrupt pins (nine external sources)
 NMI is the highest-priority interrupt, and is accepted at all times. A rising or falling edge at
the NMI pin can be selected for the NMI interrupt.
 Falling edge, rising edge, or both edge detection, or level sensing, at pins IRQ7 to IRQ0
can be selected for interrupts IRQ7 to IRQ0.
 The IRQ6 interrupt is shared by the interrupt from the IRQ6 pin and eight external interrupt
inputs (KIN7 to KIN0).
• DTC control
 DTC activation is controlled by means of interrupts.