Datasheet

Section 4 Exception Handling
Rev. 4.00 Jun 06, 2006 page 91 of 1004
REJ09B0301-0400
Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, direct transition, trap
instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority. Trap
instruction exceptions are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows.
Trace Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1.
(Cannot be used with this LSI.)
Interrupt Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
*
1
Direct transition Started by a direct transition resulting from execution of a
SLEEP instruction.
Low Trap instruction (TRAPA)
*
2
Started by execution of a trap instruction (TRAPA).
Notes: 1. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
2. Trap instruction exception handling requests are accepted at all times in the program
execution state.