Datasheet

Section 3 MCU Operating Modes
Rev. 4.00 Jun 06, 2006 page 78 of 1004
REJ09B0301-0400
3.3 Operating Mode Descriptions
3.3.1 Mode 1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled.
Ports 1 and 2 function as an address bus, port 3 function as a data bus, and part of port 9 carries
bus control signals.
3.3.2 Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use
external addresses. However, as these groups have a maximum of 16 address outputs, an external
address can be specified correctly only when the I/O strobe function of the AS/IOS pin is used.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They
can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 function as a data bus, and part of port 9 carries bus control signals.
3.3.3 Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled.
After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use
external addresses.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They
can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 function as a data bus, and part of port 9 carries bus control signals.
In products with an on-chip ROM capacity of 64 kbytes or more, the amount of on-chip ROM that
can be used is limited to 56 kbytes.