Datasheet

Section 3 MCU Operating Modes
Rev. 4.00 Jun 06, 2006 page 76 of 1004
REJ09B0301-0400
3.2.4 Serial Timer Control Register (STCR)
7
—
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
ICKS0
0
R/W
2
—
0
R/W
1
ICKS1
0
R/W
Bit
Initial value
Read/Write
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), an on-chip flash memory control (in F-ZTAT versions),
and also selects the TCNT input clock. For details of functions other than register access control,
see the descriptions of the relevant modules. If a module controlled by STCR is not used, do not
write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: Do not write 1 to this bit.
Bits 6 and 5—I
2
C Transfer Select (IICX1, IICX0): These bits control the operation of the I
2
C
bus interface when the on-chip IIC option is included. For details, see section 16.2.7, Serial Timer
Control Register (STCR).
Bit 4—I
2
C Master Enable (IICE): Controls CPU access to the I
2
C bus interface data registers
and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and
control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL),
and the SCI control registers (SMR, BRR, and SCMR).