Datasheet

Section 2 CPU
Rev. 4.00 Jun 06, 2006 page 67 of 1004
REJ09B0301-0400
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
φ
Bus cycle
T1
Address
Read data
Write data
Read
access
Write
access
Figure 2.17 On-Chip Memory Access Cycle
Bus cycle
T1
UnchangedAddress bus
AS
RD
WR
Data bus
φ
High
High
High
High impedance
Figure 2.18 Pin States during On-Chip Memory Access